Scalability of the RAMpage memory hierarchy
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Authors
Machanick, P
Issue Date
2000
Type
Article
Language
en
Keywords
Memory hierarchy , Memory wall , Caches , Computer system performance simulation
Alternative Title
Abstract
The RAMpage memory hierarchy is an alternative to the traditional division between cache and main memory: main memory is moved up a level and DRAM is used as a paging device. As the CPU-DRAM speed gap grows, it is expected that the RAMpage approach should become more viable. Results in this paper show that RAMpage scales better than a standard second-level cache, because the number of DRAM references is lower. Further, RAMpage allows the possibility of taking a context switch on a miss, which is shown to further improve scalability. The paper also suggests that memory wall work ought to include the TLB, which can represent a significant fraction of execution time. With context switches on misses, the speed improvement at an 8 GHz instruction issue rate is 62% over a standard 2-level cache hierarchy.
Description
Citation
Machanick P (2000) Scalability of the RAMpage memory hierarchy. South African Computer Journal, Number 25, 2000
Publisher
South African Computer Society (SAICSIT)
License
Journal
Volume
Issue
PubMed ID
DOI
ISSN
2313-7835