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Browsing SAICSIT Proceedings: 1979-2001 by Author "Machanick, P"

Browsing SAICSIT Proceedings: 1979-2001 by Author "Machanick, P"

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  • Machanick, P (2001)
    Increasingly aggressive pipelining achieves diminishing returns. Simultaneous Multi-threading (SMT) attempts to exploit the fact that functional units are frequently idle. This paper argues the case for keeping the processor ...
  • Machanick, P (1998)
    The SAVoD (Scalable Architecture for Video on Demand) approach to video on demand exploits the fact that end-user latency goals are relatively modest, while increasing bandwidth is much easier than improving bandwidth. ...
  • Machanick, P (1991)
    Parallel simulation, if it is to become a mainstream technology, must become reasonably accessible to programmer s without unusual skills. Since low-cost shared memory machines are becoming an increasing possibility a ...
  • Machanick, P (1998)
    Latency goals often relate to response times seen by users, which are slow by computer standards, but scaling up to large numbers of users presents a problem. Examples include transaction-based systems and web sites. ...
  • Machanick, P; Patel, Z (2001)
    The RAMpage memory hierarchy is an alternative to the traditional division between cache and main memory: main memory is moved up a level and DRAM is used as a paging device. Earlier RAMpage work has shown that the RAMpage ...
  • Machanick, P; Salverda, P (1998)
    The RAMpage memory hierarchy is an attempt at devising a comprehensive strategy to address the growing DRAM-CPU speed gap. By moving the main memory up a level to the SRAM currently used to implement the lowest-level ...
  • Machanick, P (1998)
    A commonly accepted hierarchy of cognitive skills puts analysis and synthesis near the top, with straightforward knowledge and comprehension at the bottom. A typical Computer Science curriculum, though, usually starts ...

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