Institutional Repository

Scalability of the RAMpage memory hierarchy

Show simple item record Machanick, P 2018-06-15T07:32:23Z 2018-06-15T07:32:23Z 2000 2000
dc.identifier.citation Machanick P (2000) Scalability of the RAMpage memory hierarchy. South African Computer Journal, Number 25, 2000 en
dc.identifier.issn 2313-7835
dc.description.abstract The RAMpage memory hierarchy is an alternative to the traditional division between cache and main memory: main memory is moved up a level and DRAM is used as a paging device. As the CPU-DRAM speed gap grows, it is expected that the RAMpage approach should become more viable. Results in this paper show that RAMpage scales better than a standard second-level cache, because the number of DRAM references is lower. Further, RAMpage allows the possibility of taking a context switch on a miss, which is shown to further improve scalability. The paper also suggests that memory wall work ought to include the TLB, which can represent a significant fraction of execution time. With context switches on misses, the speed improvement at an 8 GHz instruction issue rate is 62% over a standard 2-level cache hierarchy. en
dc.language.iso en en
dc.publisher South African Computer Society (SAICSIT) en
dc.subject Memory hierarchy en
dc.subject Memory wall en
dc.subject Caches en
dc.subject Computer system performance simulation en
dc.title Scalability of the RAMpage memory hierarchy en
dc.type Article en

Files in this item

This item appears in the following Collection(s)

Show simple item record

Search UnisaIR


My Account