A Virtual Multiprocessor Computer Design

Abstract

This paper describes computer design which 'would achieve a high instruction throughput rate on a relatively modest amount of hardware. It is based on multiprogramming the CPU at a sub-instruction level. The design will cope well with current computer workloads in on-line environments, where conditional branches and interrupts are frequent. The paper shows that when current high performance computers execute general jobstreams which include on-line work, they require about five machine cycles for each instruction completed, while this design should achieve close to one instruction per cycle_ This level of performance can be realized without the large investments in complexity which current high performance computers make in order to reduce the number of cycles per instruction. Furthermore, the design can be made to be program compatible with any current general purpose multi-processor.